1. Field of the Invention
The invention relates in general to a method of fabricating a capacitor, and more particularly, to a method of fabricating a dual trench capacitor with a horn region in a dynamic random access memory (DRAM).
2. Description of the Related Art
As the functions of microprocessor become more and more versatile, the program and the calculation run by a software becomes more and more sizeable. The storing capacitance of a memory is required to be larger and larger. However, as the integration of semiconductors increases, the device or circuit is shrunk according to the design rule of the fabrication process, therefore, the storing capacitance of a capacitor is reduced.
The capacitor plays as a heart of a DRAM, the more charges the capacitor can store, the less it is affected by noise, for example, soft error caused by an .alpha. particle, while accessing data. Furthermore, the frequency of refresh can be reduced. Currently, methods such as fabricating a trench-shape capacitor and reducing the thickness of the dielectric layer are used to increase the capacitance of a capacitor. The latter one is often restricted by the yield and reliability of the product.
Recently, hemispherical-grain polysilicon and stack type bottom structures are used for bottom electrode to increase the surface area. However, the cell having a stack type bottom electrode often has a height higher than the periphery circuit region, therefore, causes the problems in cell planarization and metallization.
In addition, in the fabrication process of forming a capacitor, a photo-resist layer is used to define the structure of the capacitor. During the photolithography and etching process, if misalignment occurs, the result of etching is affected, and the faulty devices or product are increased.